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160 lines
3.2 KiB
Plaintext
160 lines
3.2 KiB
Plaintext
New registers:
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I - Index, used by some of the new instructions
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D - Used by the math extension as the higher 16-bit of the 32-bit value (multiply / divide).
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NXT ($02) - NExT word
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PC = (I), I = I + 2
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8-bit mode example:
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lda (regI)
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sta ptr
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lda (regI+1)
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sta ptr+1
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inc regI
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inc regI
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jmp (ptr)
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ENT ($22) - Enter word
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RHI, I = PC + 2, PC = (PC)
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NXA ($42) - NeXt byte/word to Accumlator
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A = (I), if M=0 then I = I + 1 else I = I + 2
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example:
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lda (regI) ; 16-bit word when M flag is set
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inc regI
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.if flagM=1
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inc regI
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.fi
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TXI ($5c) - Transfer X to I
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regI = regX
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N,Z flags updated
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TIX ($dc) - Transfer I to X
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regX = regI
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N,Z flags affected
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RER ($82) - push effective RElative address to R stack
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(R) = ( PC + value ) >> 8
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(R - 1) = ( PC + value ) & 0xff
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R = R - 2
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This function works like the branches but instead of setting PC it push the result in the R stack
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REA ($44) - push address to R stack
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(R) = value >> 8
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(R - 1) = value & 0xff
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R = R - 2
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This functions simply puts the value to R stack
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8-bit mode example:
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lda #>value
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sta (regR)
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dec regR
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lda #<value
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sta (regR)
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dec regR
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REI ($54) - push indirect zp address to R stack
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(R) = (value) >> 8
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(R - 1) = (value+1) & 0xff
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R = R - 2
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Works like the previous instruction but address came from indirected zero page address
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8-bit mode example:
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lda (value)
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sta (regR)
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dec regR
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inc value
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lda (value)
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sta (regR)
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dec regR
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RHI ($0b) - push I register to R stack
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(R) = I >> 8
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(R - 1) = I & 0xff
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R = R - 2
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example:
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lda I
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sta (regR)
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dec regR
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lda I+1
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sta (regR)
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dec regR
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RLI ($2b) - pull I register from R stack
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the opposite of RHI
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RHA ($4b) - push A register to R stack
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Depends on flagM, instruction like PHA
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RLA ($6b) - pull A register from R stack
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Depends on flagM, instruction like PLA
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RHX ($1b) - push X register to R stack
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Depends on flagX, instruction like PHX
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RLX ($3b) - pull X register from R stack
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Depends on flagX, instruction like PLX
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RHY ($5b) - push y register to R stack
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Depends on flagX, instruction like PHY
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RLY ($7b) - pull y register from R stack
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Depends on flagX, instruction like PLY
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TXR ($8b) - Transfer X to R
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if flagX = 0 then R = X
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SP messed up if flagX = 1, SP = R & 0xff | X & 0xff
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TRX ($ab) - Transfer R to X
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X = R
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N,Z flags affected
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TXI ($5c) - Transfer X to I
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I = X
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N,Z flags affected
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TIX ($dc) - Transfer I to X
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X = I
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N,Z flags affected
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ORA, AND, EOR, ADC, STA, LDA, CMP, SBC
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Works like the standard 65816 r,S and (r,S),Y instructions just using R instead of S
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MUL - signed (c=0) or unsigned (c=1) MULltiply (16-bit * 16-bit)
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supports BCD mode
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DIV - signed (c=0) or unsigned (c=1) DIVide (32-bit / 16-bit)
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supports BCD mode
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ZEA - zero extend A / clear D
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D = 0
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SEA - signed extend A
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if the highest bit of A is set then D = 0xffff else D = 0
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TAD - Transfer A to D
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D = A
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N,Z flags affected
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TDA - Transfer D to A
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A = D
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N,Z flags affected
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PHD - PusH D to stack
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PLD - PulL D from stack
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Known bugs:
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- Stack pointers wrong (TSX,TXS) comparing it to a real 65xx based cpu
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- the default SP is $0200 instead of $01ff
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